1. Field of the Invention
The present invention relates, in general, to input/output (I/O) circuits, and, more particularly, to an I/O circuit that is isolated from noise occurring at a predictable time after a state change.
2. Relevant Background
Digital circuits receive and process logic signals. These logic signals comprise two or more "states" or logic levels where each state is typically represented by a unique voltage. Most digital circuits are binary having two states (i.e., logic HIGH and logic LOW) represented by two voltages. To conserve power, increase circuit density on chips and increase switching speed of the logic circuits, there is a trend to reduce the span between the two voltages. Commonly available circuits use 3.3 V and 0.0 V power supply busses allowing a span between logic levels of around 3 V.
A fundamental capability of any logic circuit is its ability to distinguish or discriminate between the voltage representing each of the logic states. In the case of binary logic, the logic signals can theoretically be distinguished by comparison to a reference the span between logic level voltages decreases, however, this comparison becomes more problematic. Also, when more than two logic levels are used, the difference between adjacent logic level voltages is difficult to distinguish. In these circuits, the logic level discriminator becomes increasingly sensitive to noise, particularly noise that affects the voltage on the power supply busses.
For example, in a dynamic random access memory (DRAM) circuit, an entire row of memory cells is addressed at one time using a row address line. Each row address line extends across a memory chip to hundreds of memory circuits. The row address line has significant capacitance and the memory circuits themselves are a significant capacitive load. Hence, the row address operation causes significant current flow in the power supply bus wiring and corresponding current resistance (IR) voltage loss in the bus wiring. The voltage loss results in incorrect discrimination between logic levels for a brief period of time after the row address signal occurs unless steps are taken to ensure that the power supply busses are not loaded by the signal transition.
Previous circuits attempt to solve the bus loading problem by independently routing power (V.sub.DD) and ground (V.sub.SS) bussing about the integrated circuit. In this manner, circuits that are used to discriminate logic levels are coupled to voltage supply busses that are separate from the loaded supply busses. However, independent routing consumes more chip area resulting in larger, more costly chips. Also, independent routing can reduce overall power and ground effectiveness.
Another solution is to use Schmitt triggers in the discriminator circuits. A Schmitt trigger is essentially a comparator with hysteresis. Schmitt triggers, however, merely reduce noise sensitivity, not eliminate it. Because they introduce hysteresis they reduce the input level margin making them less effective as the voltage span between logic levels decreases.
Another solution is to use "de-glitch" or "de-bounce" circuits. These circuits essentially add a delay in series with the input before a valid output signal is made available. For example, in a memory circuit a de-glitch circuit would not make a data output valid until after a delay sufficient for the power supply busses to stabilize. While these circuits ensure valid data output, they by definition add delay and slow response of the system. Hence, a need remains for a input/output circuit that is insensitive to noise yet does not add excessive delay or decrease the input level margin.